Shallow trench isolation (STI) is a commonly used process consisted of three main steps, namely, etching, filling and planarizing. In a general case, a mask layer is first formed on the surface of a substrate and thereafter is used as an etching mask to form one or more trenches in the substrate. Next, a pad oxide layer for protecting the substrate from being damaged during a subsequent step of filling the trenches is formed over the inner surface (including the bottom face and two side faces) of each trench before the trenches are filled. Then a planarization or etching method is employed to remove the mask layer after the trenches are filled.
In some applications of the STI process, such as that in the formation of a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), the STI process may further include a step of forming inner sidewalls over the side faces of each trench after the formation of the trenches. These inner sidewalls can serve as barriers to prevent ions from entering the underlying portions of the silicon substrate on both sides of the trenches during a subsequent step of ion implantation for forming pseudo buried layers under the bottoms of the trenches. After the ion implantation step, these inner sidewalls are removed followed by steps of filling and planarizing the shallow trenches.
The foregoing “inner-sidewalls-involved” STI process will at least include a dry etching step for forming the inner sidewalls, a wet etching step for removing the inner sidewalls and another wet etching step for removing the mask layer. During these dry and wet etching steps, there may be damages to the pad oxide layer and even to the underlying silicon, which will lead to significant electrical leakage, or crystal defects after a high temperature treatment. Such crystal defects may further lead to failure of the device.
FIG. 1 is a schematic representation of device defects generated after an inner-sidewalls-involved STI process is carried out according to the prior art. As shown in the figure, due to the corrosion of the wet etching step of the STI process, obvious damages are present in boundary portions of the pad oxide layer 3 where the shallow trench 2 and the top surface of the silicon substrate 1 contact with each other. As a result, during the subsequent step of forming a metal silicide on the top surface of the silicon substrate 1, a portion of the silicide 4 (as indicated by the dash-line circles in FIG. 1) grows downward into the boundary portions of the pad oxide layer 3. This portion of the silicide may spike the below pn junction and cause a high leakage current.